Phase change materials in non-volatile storage

After revolutionizing the technology of optical data storage, phase change materials are being adopted in non-volatile semiconductor memories. Their success in electronic storage is mostly due to the unique properties of the amorphous state where carrier transport phenomena and thermally-induced phase change cooperate to enable high-speed, low-voltage operation and stable data retention possible within the same material. This paper reviews the key physical properties that make this phase so special, the quantitative framework of cell performance, and the future perspectives of phase-change memory devices at the deep nanoscale

A 64-Channel 965-μW Neural Recording SoC with UWB Wireless Transmission in 130-nm CMOS

This brief presents a 64-channel neural recording system-on-chip (SoC) with a 20-Mb/s wireless telemetry. Each channel of the analog front end consists of a low-noise bandpass amplifier, featuring a noise efficiency factor of 3.11 with an input-referred noise of 5.6 μVrms in a 0.001- to 10-kHz band and a 31.25-kSps 6-fJ/conversion-step 10-bit SAR analog-to-digital converter. The recorded signals are multiplexed in the digital domain and transmitted via an 11.7% efficiency pulse-position modulation ultrawideband transmitter, reaching a transmission range in excess of 7.5 m. The chip has been fabricated in a 130-nm CMOS process, measures 25 mm2, and dissipates 965 μW from a 0.5-V supply. This SoC features the lowest power per channel (15 μW) and the lowest energy per bit (48.2 pJ) among state-of-the-art wireless neural recording systems with a number of channels larger than 32. The proposed circuit is able to transmit the raw neural signal in a large bandwidth (up to 10 kHz) without performing any data compression or losing vital information, such as local field potentials

Comprehensive Investigation of Statistical Effects in Nitride Memories-Part I: Physics-Based Modeling

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Three-Dimensional Simulation of Charge-Trap Memory Programming-Part I: Average Behavior

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Semi-Analytical Model for the Transient Operation of Gate-All-Around Charge-Trap Memories

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The race of phase change memories to nanoscale storage and applications

reserved2The successful development of phase change memory technology (PCM) has been one of the most relevant novelties in the field of semiconductor memories of the last years. PCM products at the 45 nm node are being manufactured, mainly driven by applications in cellular phones. In the coming years, the consolidated know-how accumulated over five decades of research activities and more than ten years of industrial experience will further drive the race of resistive storage components to nanoscale, supporting the development of energy-aware, optimized memory systems for both stand-alone and embedded applications. This paper provides an overview of the most recent developments on phase change physics and technology, pointing out the key topics requiring additional investigation and further understandingA.L. Lacaita; A. RedaelliLacaita, ANDREA LEONARDO; Redaelli, Andre

Background adaptive linearization of high-speed digital-to-analog converters

This paper presents a digital background linearization technique for high-speed Nyquist-rate digital-to-analog Converters (DACs), based on the use of a least-mean-square (LMS) multipath adaptive filter that continuously measures and cancels non-linearity arising from static errors. In contrast to previously-published correlation-based techniques, the proposed method is not limited to the cancellation of component mismatches, but it performs the correction of the overall static characteristic regardless of the source of non-linearities. It requires only an additional low-speed accurate DAC and moderate digital hardware complexity, avoiding the need for a multibit analog-to-digital converter. The effectiveness of the proposed technique applied to a current-steering DAC suggests that it could be useful to overcome the typical high-speed DAC trade-off, allowing the elimination of static non-linearity errors without sacrificing dynamic performances

A Single-Inductor Two-Step-Mixing Injection-Locked Frequency Divider by Four with Concurrent Tail-Injection

The paper presents a novel single-inductor injection- locked frequency divider (ILFD) by four. The topology improves the ILFD by four two-step-mixing circuit by introducing an additional tail-injection path driven by a common-mode tone at the input frequency. This new path adds a further contribution to the injection current thus boosting the locking-range. When compared with the single-inductor two-step-mixing ILFD by four at the same operating conditions and CMOS process, the novel topology shows a 67% locking-range enhancement. The novel scheme is then exploited to design a 20-GHz divide-by-four prescaler in a standard 65-nm LP CMOS process. With a 0.4- V input signal amplitude, the circuit shows a 22% lock range at 4.6 mW DC power consumption, which is competitive with state-of-art ILFDs, which, however, use two or more inductor

A Low-Power and Wide-Locking-Range Injection-Locked Frequency Divider by Three with Dual-Injection Divide-by-Two Technique

A novel low-power and wide-locking-range divide- by-three injection-locked frequency divider with single inductor is presented in this paper. The classical topology with divide- by-two locking scheme is improved via the introduction of an extra tail-injection driven by the central node of the floating- source direct injector. This new concept is applied to the design of a 15GHz divider-by-three in a standard 65-nm LP CMOS technology, which reaches, in post-layout simulations at 100°C temperature, a 23.6% locking range at an input power of 0dBm and DC power consumption of 1.56mW. The divider figure of merit together with the compact size of only 0.09mm2 are best in class for injection-locking dividers with single inductor and same input power. The figure of merit is also very close to the values reached by the best injection-locking dividers-by-three, that, however, use more inductors